In the 1990s, the beginning of the ULSI era, the most important factor achieving the ULSI complexity has been the continued reduction of the minimum device-feature length (gate, source and drain regions in MOS devices). The reduction in feature length and related dimensions has resulted in promoting the rapid growth in the number of components per MOSFET chip (the unit cost per function reduction) and improving of device speed (which varies inversely approximately with the square of feature length).
However, as a device is scaled from one micron down to the submicron size or beyond, it may suffer more stringent problems. For example, hot carriers effect and punchthrough effect are two of the major constraints in CMOS transistor scaling. Further, parasitic resistance and capacitance in the scaled device structure must be avoided.
Another limiting factor for devices with submicron dimensions is the conductivity of the source/drain regions and the poly-gate. For example, the sheet resistance of diffusion regions increases from 25 .OMEGA./sq--in a 1 .mu.m technology to 50 .OMEGA. sq--in a 0.5 .mu.m technology. A self-aligned silicide technology, namely salicide, has been developed which involves the formation of silicide on poly-silicon gate, source and drain contact simultaneously. The salicide process can provide not only low-sheet resistance for S/D regions and for gate electrodes in MOS devices but also a very clean silicide-silicon interface. Further, it does not require any additional lithography and etching. In addition, the alignment was predetermined.
Another critical issue accompanying the feature size of MOSFET scale down and degrading significantly the device performance is the electrostatic discharge (ESD). The ESD may be easily conducted through the input/output and power lead connections into the internal devices to destroy the devices. For example, a high voltage can be accidentally applied to the pins of the IC package by a person while handling, causing the breakdown of the gate oxide of the devices. Thus, it is imperative that a built-in protective ESD circuitry be formed simultaneously with the functional transistors.
However, silicided S/D regions and the LDD structures can degrade the ESD performance of the gate-controlled breakdown structure. As a result, the ESD protection structures can be rendered largely ineffective by the silicided process. Chen proposed that "Shallower junctions and thicker salicide have a negative impact on the ESD capability of a process," in an article appearing at page 212 of the Proceedings of the 10.sup.th EOS/ESD Symposium (1988).
In an article appearing at page 893 of the IEDM Technical Digest (1996), Amerasekera et al. investigated the relationship between the current gain .beta. of a self-biased lateral NPN (parasitic bipolar in a NMOS) transistor and the ESD performance, and found that devices with lower .beta. are observed to have lower ESD performance. Further, the authors also suggested that .beta. is found to be strongly influenced by the effective drain/source diffusion depth below the salicide which is determined by the implant energy as well as by the amount of active diffusion consumed in silicidation. Thus, it is essential to develop a salicide process with an ESD preventive circuitry and the ULSI devices being fabricated at the same time giving the least influence on ESD performance.
On the other hand, as linewidths are narrowed to submicron size, the lithography also becomes a limiting factor. For example, decreasing the wavelength (.lambda.) of the optical source and increasing numerical aperture (NA) are logical approaches to improve resolution. However, they decrease the depth of focus (DOF). See the equation given in the reference by C. Y. Chang and S. M. Sze, "ULSI technology," (McGraw-Hill Book Co. (1996) p. 270): EQU DOF=.+-..lambda./2(NA).sup.2
The DOF corresponds to the height of the largest window or equivalently to the height of photoresist. It is, therefore, essential to decrease the number of lithography or to find an effective mask formed at a lower temperature with minimum thickness that can block the unwanted icons during implanting. A liquid phase deposition (LPD) oxide layer is one of the best candidates that can satisfy such conditions.
The LPD technology as suggested by Homma, et al., in J. Electrochem. Soc. 140, (1993) p. 2410, utilizes supersaturated hydrofluosilicic acid and H.sub.2 SiF.sub.6 aqueous as a source liquid. The LPD-SiO.sub.2 layers can be selectively formed on chemical vapor deposition (CVD) SiO.sub.2 underlayers in the trenches between photoresist patterns or tungsten wiring with photoresist as a mask without destroying the photoresist. Besides, the lower reaction temperature is required for forming LPD-SiO.sub.2 layers. Other benefits obtained from the LPD-SiO.sub.2 layers include the fact that it can more effectively prevent the ion penetrated through the oxide layer than through the photoresist during ion implantation. Thus, no additional mask is needed.